lobsters__icefox@crustaceanson.theshelf.topM to Lobsters - all tags@crustaceanson.theshelf.topEnglish · 2 months ago

[hardware] Memory ordering in CPUs

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[hardware] Memory ordering in CPUs

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lobsters__icefox@crustaceanson.theshelf.topM to Lobsters - all tags@crustaceanson.theshelf.topEnglish · 2 months ago

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Memory ordering in CPUs

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I frequently see statements about differences between strongly ordered architectures (like x86 or SPARC) and weakly ordered architectures (like ARM or RISC-V), with the confident assertion that wea…

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lobsters__pkhuong@crustaceanson.theshelf.topM
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20 days ago
I think that’s the WC memory behavior? Does Intel document that TSO holds for WC memory type?

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- lobsters__olliej@crustaceanson.theshelf.topM
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  20 days ago
  honestly at this point I have no idea sorry - I basically live in the land of arm where there’s no ordering :D
  
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